Memory device

ABSTRACT

The present invention provides a memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section that changes a bit width of the parallel data. This memory device connects one external terminal to the serial-parallel conversion section and another external terminal to the parallel-serial conversion section when access using a serial interface is performed. On the other hand, the memory device connects a plurality of external terminals to the parallel-parallel conversion section when access using a parallel interface is performed, thereby enabling the memory device to occasionally realize parallel transfer of data while using a conventional package.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon, and claims the benefit of priority from,earlier Japanese Patent Application No. 2004-315406 filed on Oct. 29,2004 so that its entire disclosure, including specification, claims,drawings, and abstract, is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a memory device that selectively acceptsaccesses using a serial interface and accesses using a parallelinterface.

2. Description of the Related Art

A memory device, such as a flash memory, uses an architecture that iscapable of accepting access using a simple four-wire serial interface.The memory device using a serial interface is usually incorporated intoan 8-pin or 16-pin chip package, for example, as shown in FIG. 6.Therefore, compared with a memory device using a parallel interface, theserial interface equipped memory device can be easily downsized andaccordingly the cost of the chip package can be reduced.

For example, when an 8-pin chip package is used, four of the eight pinsare allocated to terminals of a four-wire serial interface, i.e. anaddress/data input terminal (SI), a data output terminal (SO), a chipselect terminal (CS#), and a system clock input terminal (SCK), while 2pins are allocated to power source terminals (VDD and VSS). Theremaining pins, i.e. two pins, are allocated to control terminals, suchas a write protect terminal that determines allowance when an access forwriting/erasing is received, a reset terminal that stops processing inresponse to an interrupt request, or a hold terminal that interrupts theprocessing and holds the condition.

FIG. 7 shows a memory device 100 equipped with a serial interface thatincludes an address buffer/latch section 10, a control logic section 12,a data register 14, an X decoder 16, a Y decoder 18, a memory array 20,a serial-parallel conversion section 22, and a parallel-serialconversion section 24.

FIG. 8 is a timing diagram showing the control processing for readingdata out of the memory device 100.

First, the electrical potential of the chip select terminal (CS#) ischanged to a low level to select the memory device 100 as an object tobe accessed. In response to the potential change of the chip selectterminal (CS#) to the low level, the control logic section 12 bringsother sections into a command receivable state.

Next, a data reading command (i.e. 03h shown in FIG. 8), that instructsreading of data, is input from the address/data input terminal (SI). Thecommand is arranged, for example, as 8-bit data and is serially input tothe serial-parallel conversion section 22, bit by bit, in synchronismwith a system clock input from the system clock input terminal (SCK).The serial-parallel conversion section 22 converts the command from theserial data into parallel data corresponding to a bit width of aninternal bus (e.g. 8 bits). The converted parallel data is sent to thecontrol logic section 12.

The control logic section 12 analyzes the command. For example, when theinput command is a data reading command (03h), the control logic section12 brings other sections into an address value receivable state.

Next, an address value (Add.) is input from the address/data inputterminal (SI). The address value is, for example, expressed as 24-bitserial data and is input to the serial-parallel conversion section 22,bit by bit, in synchronism with the system clock. The serial-parallelconversion section 22 successively converts the address value from theserial data into parallel data corresponding to the bit width of theinternal bus (e.g. 8 bits). The control logic section 12 causes theserial-parallel conversion section 22 to successively transfer theaddress value, being converted into the parallel data, to the addressbuffer/latch section 10.

The address buffer/latch section 10, when the address value has beenreceived, outputs a control signal to each of the X decoder 16 and the Ydecoder 18 to identify a corresponding memory element in the memoryarray 20, and the data stored in this memory element is read out. Thereadout data is stored, via the Y decoder 18, into the data register 14.The parallel-serial conversion section 24 converts the data stored inthe data register 14 into serial data and outputs the converted serialdata from the data output terminal (SO) in synchronism with the systemclock.

The address buffer/latch section 10 successively increases the addressvalue so that the memory array 20 can successively read the data out ofa memory element identified by the next address value.

However, according to such a memory device using a four-wire serialinterface, the input/output of address value and data is performed by1-bit serial communication, and accordingly the transfer rate is verylow compared with that of the memory device using a parallel interface.

SUMMARY OF THE INVENTION

In view of the foregoing problems in the prior art technique, it is anobject of the present invention to provide a high performance memorydevice.

To accomplish the above and other related objects, the present inventionprovides a memory device equipped with a memory array that includes aplurality of memory elements respectively identified by unique addressvalues, wherein the memory device reads a data out of a memory elementidentified by an address value when the address value is input from atleast one of external terminals, and outputs the readout data to atleast one of the external terminals. The memory device of this inventionincludes a serial-parallel conversion section, a parallel-serialconversion section, a parallel-parallel conversion section, and amultiplexer. The serial-parallel conversion section has the capabilityof converting serial data into parallel data. The parallel-serialconversion section has the capability of converting parallel data intoserial data. The parallel-parallel conversion section has the capabilityof changing a bit width of the parallel data. The multiplexer canconnect at least some of the external terminals to one of theserial-parallel conversion section, the parallel-serial conversionsection, and the parallel-parallel conversion section. The multiplexer,when access using a serial interface is performed, connects one of theexternal terminals to the serial-parallel conversion section andconnects another of the external terminals to the parallel-serialconversion section. Furthermore the multiplexer, when access using aparallel interface is performed, connects a plurality of the externalterminals to the parallel-parallel conversion section.

The above and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription of an exemplary embodiment with reference to the attacheddrawings

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate a preferred embodiment of theinvention and, together with the description, serve to explain theprinciples of the invention, in which:

FIG. 1 is a block diagram showing the arrangement of a memory device inaccordance with a preferred embodiment of the present invention;

FIG. 2 is a diagram showing the arrangement of a multiplexer inaccordance with the preferred embodiment of the present invention;

FIG. 3 is a diagram showing the allocation of pins of the memory devicein a case where access using a parallel interface is performed;

FIG. 4 is a timing diagram showing the data read out processing via theparallel interface in accordance with the preferred embodiment of thepresent invention;

FIG. 5 is a timing diagram showing the processing for switching from theparallel interface to the serial interface in accordance with thepreferred embodiment of the present invention;

FIG. 6 is a diagram showing the allocation of pins of a conventionalmemory device in a case where access using a serial interface isperformed;

FIG. 7 is a block diagram showing the arrangement of a memory device ofthe background art; and

FIG. 8 is a timing diagram showing the processing for reading out datavia the serial interface according to the memory device of thebackground art.

DESCRIPTION OF A PREFERRED EMBODIMENT

Hereinafter, a preferred embodiment of the present invention will beexplained with reference to attached drawings.

FIG. 1 shows a memory device 200 in accordance with a preferredembodiment of the present invention, which includes an addressbuffer/latch section 30, a control logic section 32, a data register 34,an X decoder 36, a Y decoder 38, a memory array 40, a serial-parallelconversion section 42, a parallel-serial conversion section 44, aparallel-parallel conversion section 46, and a multiplexer 48.

The memory device 200 uses a package similar to that of a conventionalmemory device using a serial interface. The memory device 200 isequipped with a multiplexer 48 that is capable of switching terminalconnection in response to each of access using a serial interface andaccess using a parallel interface.

As shown in FIG. 2, the multiplexer 48 is equipped with a plurality ofchangeover switches 48 a. The multiplexer 48, upon receipt of aswitching control signal from the control logic section 32, connectsrespective external terminals of a chip package to one of theserial-parallel conversion section 42, the parallel-serial conversionsection 44, and the parallel-parallel conversion section 46.

For example, in a case where an 8-pin chip package is used, thechangeover switches 48 a are connected to left-hand terminals whenaccess using a serial interface is performed. In this case, theallocation of respective terminals is identical with that shown in FIG.6. More specifically, the data output terminal (SO) is connected to theparallel-serial conversion section 44. The address/data input terminal(SI) is connected to the serial-parallel conversion section 42. Thefirst control terminal (C0) and the second control terminal (C1) areconnected to the control logic section 32.

On the other hand, the changeover switches 48 a are connected toright-hand terminals when access for reading data via the parallelinterface is performed. In this case, the terminals are allocated, forexample, as shown in FIG. 3. The data output terminal (SO) is allocatedto a fourth data input/output terminal (SIO3). The first controlterminal (C0) is allocated to a third data input/output terminal (SIO2).The second control terminal (C1) is allocated to a second datainput/output terminal (SIO1). Finally, the address/data input terminal(SI) is allocated to a first data input/output terminal (SIO0). Withthis arrangement, access using the parallel interface becomes feasible.Namely, all of the data output terminal (SO), the address/data inputterminal (SI), the first control terminal (C0) and, the second controlterminal (C1) are connected to the parallel-parallel conversion section46.

Hereinafter, the data read out processing using a serial interface, thedata read out processing using a parallel interface, and the processingfor resuming the processing using the serial interface will besuccessively explained.

Data Read Out Processing Via Serial Interface

The memory device 200, under normal conditions, accepts accesses using aserial interface. The changeover switches 48 a of the multiplexer 48 areconnected to the left-hand terminals so that respective terminals areallocated as shown in FIG. 6.

Accordingly, like the above-described conventional memory device, theprocessing for reading the data out of the memory device 200 is carriedout according to the timing diagram shown in FIG. 8. This processing isalready explained for the above-described conventional memory device,and accordingly will not be explained hereinafter.

Data Read Out Processing Via Parallel Interface

Access using the parallel interface is carried out according to thetiming diagram shown in FIG. 4. Under initial conditions, the changeoverswitches 48 a of the multiplexer 48 are connected to the left-handterminals so that the terminals are allocated as shown in FIG. 6.

First, the electrical potential of the chip select terminal (CS#) ischanged to a low level to select the memory device 200 as an object tobe accessed. In response to the potential change of the chip selectterminal (CS#) to the low level, the control logic section 32 bringsother sections into a command receivable state.

Next, a data reading command (i.e. D4h shown in FIG. 4), that instructsreading of data via the parallel interface, is input from theaddress/data input terminal (SI). The command is arranged, for example,as 8-bit data and is serially input to the serial-parallel conversionsection 42, bit by bit, in synchronism with a system clock input fromthe system clock input terminal (SCK). The serial-parallel conversionsection 42 converts the command from the serial data into parallel datacorresponding to a bit width of an internal bus (e.g. 8 bits). Theconverted parallel data is sent to the control logic section 32.

The control logic section 32 analyzes the command. When it has receivedthe command (D4h) instructing data reading via the parallel interface,the control logic section 32 brings other sections into an address valuereceivable state and causes the multiplexer 48 to switch the changeoverswitches 48 a to the right-hand terminals. With this operation, all ofthe data output terminal (SO), the address/data input terminal (SI), thefirst control terminal (C0), and the second control terminal (C1) areconnected to the parallel-parallel conversion section 46. The dataoutput terminal (SO) is allocated to the fourth data input/outputterminal (SIO3). The first control terminal (C0) is allocated to thethird data input/output terminal (SIO2). The second control terminal(C1) is allocated to the second data input/output terminal (SIO1).Finally, the address/data input terminal (SI) is allocated to the firstdata input/output terminal (SIO0).

In this case, it is preferable that the switching of the multiplexer 48is performed at the time when the electrical potential of the chipselect terminal (CS#) is changed to the low level after it has returnedonce to a high level. It is also preferable that the switching ofmultiplexer 48 is performed after the control logic 32 has counted up apredetermined number of system clocks in synchronism with each systemclock input from the system clock terminal (SCK).

Next, an address value (Add.) is input from a total of four datainput/output terminals (SIO0 to SIO3), 4 bits at a time, simultaneouslyin parallel with each other. The address value is, for example,expressed as a 24-bit parallel data and is input to theparallel-parallel conversion section 46, 4 bits at a time, insynchronism with the system clock. The parallel-parallel conversionsection 46 successively converts the address value into parallel datacorresponding to the bit width of the internal bus (e.g. 8 bits). Thecontrol logic section 32 causes the parallel-parallel conversion section46 to successively transfer the address value, being converted into theparallel data having the bit width of the internal bus, to the addressbuffer/latch section 30.

The address buffer/latch section 30, when receiving the address value,outputs a control signal to each of the X decoder 36 and the Y decoder38 to identify a corresponding memory element in the memory array 40,and the data stored in this memory element is read out. The readout datais stored, via the Y decoder 38, in the data register 34. Theparallel-parallel conversion section 46 converts the data stored in thedata register 34, having the bit width of the internal bus, intoparallel data of 4 bits, and outputs the converted parallel data fromfour data input/output terminals (SIO0 to SIO3) in synchronism with thesystem clock.

The address buffer/latch section 30 successively increases the addressvalue so that the memory array 40 can successively read the data out ofa memory element identified by the next address value.

According to this embodiment, the input/output of address value and datais performed in synchronism with the system clock. However, it ispossible to use a double data rate (DDR) or other high-speed transfertechnique.

Processing for Resuming Access Via Serial Interface

The processing for switching from access using the parallel interface toaccess using the serial interface will be explained hereinafter withreference to FIG. 5. The electrical potential of the chip selectterminal (CS#) is returned to the high level to cancel the selection ofthe memory device. Then, the electrical potential of the chip selectterminal (CS#) is again changed to the low level. The pulse input tothis chip select terminal (CS#) is used as a trigger to execute theprocessing for receiving input of a new command.

Namely, the control logic section 32 brings the memory device 200 into acommand input receivable state. Subsequently, the command is input asparallel data, which are input simultaneously 4 bits at a time, fromfour data input/output terminals (SIO0 to SIO3).

The command is, for example, expressed as 8-bit data and is input to theparallel-parallel conversion section 46 as parallel data, 4 bits at atime, in synchronism with the system clock. The parallel-parallelconversion section 46 converts the command into data having the bitwidth of the internal bus (e.g. 8 bits) and transmits the converted datato the control logic section 32.

The control logic section 32 analyzes the command. When the commandinstructs return to access using the serial interface, the control logicsection 32 causes the multiplexer 48 to switch the changeover switches48 a to left-hand terminals. With this operation, ordinary access usingthe serial interface becomes feasible.

In this case, it is preferable for the switching of multiplexer 48 to beperformed at the time when the electrical potential of the chip selectterminal (CS#) is changed to the low level after it is has been returnedto the high level. It is also preferable for the switching ofmultiplexer 48 to be performed after a predetermined waiting time haspassed in synchronism with the system clock input from the system clockterminal (SCK).

As described above, according to this embodiment, the size of thepackage is substantially the same as that of a conventional memorydevice using a serial interface. Meanwhile, it becomes possible torealize a memory device having the capability of occasionally acceptingaccess using the parallel interface.

While the present invention has been described with reference to anexemplary embodiment, it is to be understood that the invention is notlimited to the disclosed exemplary embodiment. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all modifications, equivalent structures and functions.

1-4. (canceled)
 5. A memory device, comprising a first terminal, asecond terminal, a third terminal, and a control logic section connectedto the first terminal; wherein in a state in which the first terminalfunctions as an address/data input terminal (SI), in which the secondterminal functions as a data output terminal (SO), and in which thethird terminal functions as a control terminal (CS), when the controllogic section receives, by an input via the first terminal, a datareadout command from a parallel interface, at least two of the firstterminal, the second terminal, and the third terminal function asinput/output terminals (I/O).
 6. The memory device according to claim 5,further comprising a chip select terminal; wherein after the controllogic section receives the data readout command from the parallelinterface, at least two of the first terminal, the second terminal, andthe third terminal function as the input/output terminals (I/O) at atiming at which the chip select terminal is placed in an active statesubsequent to being once placed in a non-active state.
 7. The memorydevice according to claim 5, further comprising a system clock terminal;wherein after the control logic section receives the data readoutcommand from the parallel interface, at least two of the first terminal,the second terminal, and the third terminal function as the input/outputterminals (I/O) after a count of system clocks input into the systemclock terminal reaches a predetermined number.
 8. A memory device,comprising a first terminal, a second terminal, a third terminal, and acontrol logic section connected to the first terminal; wherein in astate in which at least two of the first terminal, the second terminal,and the third terminal function as input/output terminals (I/O), whenthe control logic section receives, by an input via a terminalfunctioning as the input/output terminal, a data readout command from aserial interface, the first terminal functions as an address/data inputterminal (SI), the second terminal functions as a data output terminal(SO), and the third terminal functions as a control terminal (CS). 9.The memory device according to claim 8, further comprising a chip selectterminal; wherein after the control logic section receives the datareadout command from the serial interface, at a timing at which the chipselect terminal is placed in an active state subsequent to being onceplaced in a non-active state, the first terminal functions as theaddress/data input terminal (SI), the second terminal functions as thedata output terminal (SO), and the third terminal functions as thecontrol terminal (CS).
 10. The memory device according to claim 8,further comprising a system clock terminal; wherein after the controllogic section receives the data readout command from the parallelinterface, subsequent to when a count of system clocks input into thesystem clock terminal reaches a predetermined number, the first terminalfunctions as the address/data input terminal (SI), the second terminalfunctions as the data output terminal (SO), and the third terminalfunctions as the control terminal (CS).